1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to write wirings of a magnetic random access memory (MRAM) which uses tunneling magneto resistive (TMR) elements as memory elements.
2. Description of the Related Art
In recent years, MRAM cells have been proposed which utilize the tunneling magneto resistive (hereinafter abbreviated as TMR) effect.
FIG. 17 shows an equivalent circuit diagram of a prior-art semiconductor device. FIG. 18 is a schematic sectional view of a TMR element.
As shown in FIG. 18, a bit line 21 and a pair of word lines 19 and 20 are arranged so that they intersect with each other. At the intersection of the bit line 21 and the write word line 19 is placed a TMR element 20, which has one end connected to the bit line 21 and one other end connected to a transistor 13. The gate electrode of the transistor 13 forms the read word line 26.
The TMR element 20 is formed into a three-layer structure consisting of two magnetic layers and a non-magnetic layer sandwiched between the magnetic layers. That is, as shown in FIG. 18, the TMR element 20 is formed from a magnetization fixing layer 41 connected with a lower electrode 17, a magnetic recording layer 43 connected with the bit line 21 by an upper electrode (not shown), and a thin tunnel junction layer 42 sandwiched between the upper and lower layers.
The magnetization fixing layer 41, formed from an antiferromagnetic layer and ferromagnetic layer, is referred to as the pin layer because the magnetization is fixed in one direction. On the other hand, the magnetic recording layer 43, consisting of a ferromagnetic layer, is referred to as the memory layer because the direction of magnetization can be changed freely and hence data can be stored. The direction of magnetization in the magnetic recording layer 43 can be changed by a composite magnetic field resulting from a current in the bit line 21 and a current in the write word line 19.
FIG. 19 illustrates, in sectional view, a prior-art semiconductor memory device. As shown in this diagram, a semiconductor substrate (or a well) 11 of, for example, p-type conductivity is selectively formed with device isolation regions 12 of shallow trench isolation (STI) structure and MOSFETs 13 having n-type source/drain regions 14. The gate electrode of each MOSFET 13 forms a read word line 26. First contacts 16a are formed in an insulating layer 15 formed over the semiconductor substrate 11 so that they connect to the source/drain regions 14. First wirings 17a are formed on the first contacts 16a. Likewise, second, third and fourth contacts 16b, 16c and 16d and second, third and fourth wirings 17b, 17c and 17d are formed in the insulating layer 15. Part of the first wirings 17a form ground (GND) lines 18. Part of the third wirings 17c form write word lines 19a, 19b and 19c. To each of the fourth wirings 17d is connected a TMR element 20 which is connected at the other end to a bit line 21.
Next, the read/write operation of the semiconductor memory device will be described briefly.
To write a 1 or 0 into the TMR element 20, the corresponding word line 19 and bit line 21 are selected and driven, so that currents flow in the selected word and bit lines to produce magnetic fields. Thereby, the selected cell (TMR element), placed at the intersection of the selected word and bit lines, is subjected to a composite magnetic field which is of such intensity as to allow the reversal of magnetization to occur in the TMR element 20. As a result, data is written into the selected TMR element.
When the magnetization fixing layer 41 and the magnetic recording layer 43 are magnetized in the same direction, the resistance of the tunneling junction layer 42 is minimized. This state can be used to store a 1. On the other hand, when the magnetization fixing layer 41 and the magnetic recording layer 43 are magnetized in opposite directions, the resistance of the tunneling junction layer 42 is maximized. This state can be used to store a 0. That is, in the MRAM, the difference in the tunnel resistance is used to store binary digits of one and zero.
To read information written into the TMR element 20, on the other hand, the corresponding read word line 26 and bit line 21 are selected, whereupon current flows from the bit line 21 through the corresponding MOSFET 13 to the corresponding ground line 18. The peripheral circuit can discriminate between stored information 1 and 0 by sensing (the magnitude of the current which depends on) the tunnel resistance.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of first wirings extending in a first direction; a plurality of memory elements connected with the first wirings; a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements; and first transistors or diodes connected between two adjacent of the second wirings.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of first wirings extending in a first direction; a plurality of memory elements connected with the first wirings; a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements; and second transistors or diodes connected between two adjacent of the second wirings.